1. Field of the Invention
The present invention relates to a startup circuit and power supply circuit, in particular to a startup circuit that raises output voltage slowly in the startup period of a power supply, avoiding fast variation of the output voltage, and to a power supply circuit including such a startup circuit.
2. Description of the Related Art
In a startup period of a power supply circuit, rising up of the output voltage can generate an inrush current. The power supply circuit in that case may fall into an overcurrent state and causes undesirable functioning of unstable startup of the power supply. Accordingly, power supply circuits are generally provided with a startup circuit with a soft starting function that reduces voltage rising up rate and prevents inrush current for achieving stable startup.
FIG. 10 is a block diagram showing an example of conventional DC to DC converter provided with a soft starting function. FIG. 11 shows waveforms of voltages in operation of the conventional DC to DC converter of FIG. 10.
The DC to DC converter comprises two semiconductor switches MH and ML series-connected between a power supply voltage VIN and the ground potential. In this example, N channel MOSFETs are used for the high side and low side semiconductor switches MH and ML. The connection point between the high side semiconductor switch MH and the low side semiconductor switch ML is connected through a series circuit of an inductor L and a smoothing capacitor CO to the ground potential. The connection point between the inductor L and the smoothing capacitor CO is connected to the output terminal of the DC to DC converter, from which an output voltage VOUT is delivered.
Between the output terminal of the DC to DC converter and the ground potential, series-connected resistors R1 and R2 are connected. The connection point between the resistors R1 and R2 is connected to an inverting input terminal of an error amplifier EA to supply a feedback signal VFB proportional to the output voltage VOUT to the error amplifier EA.
The error amplifier EA also receives an output VCS of a soft start circuit and a reference voltage VR at non-inverting terminals of the error amplifier EA, and amplifies the difference between (a) a smaller value of the output voltage VCS of the soft start circuit and the reference voltage VR and (b) the feedback signal VFB, and delivers the amplified difference from the output terminal of the error amplifier EA. The reference voltage VR is a target voltage for delivering a desired output voltage VOUT of the DC to DC converter.
The soft start circuit comprises a series circuit of a constant current circuit IS, which is a current source, and a capacitor CS for soft starting. The soft start circuit also comprises a discharging switch SW connected in parallel to the capacitor CS. When the discharging switch SW is closed, which is in an ON state of the switch, the terminal voltage of the capacitor CS becomes zero volts, which is applied to a non-inverting terminal of the error amplifier EA. When the discharging switch SW is opened, which is an OFF state of the switch, the capacitor CS is charged with a constant current from the constant current circuit IS. The terminal voltage VCS of the capacitor CS is a ramp voltage increasing on a slope, and is applied to the non-inverting terminal of the error amplifier EA
The output terminal of the error amplifier EA is connected to a non-inverting terminal of a pulse width modulation (PWM) comparator COMP, delivering an error voltage VE. To an inverting terminal of the PWM comparator COMP, connected is an output terminal of an oscillator OSC that delivers a triangular signal VOSC.
An output terminal of the PWM comparator COMP is connected to an input terminal of a logic circuit LC and delivers a PWM pulse VPWM1 to the logic circuit LC. The output terminal of the logic circuit LC is connected to input terminals of a high side driver DH and a low side driver DL, and delivers PWM pulses VPWM2 which are logically reversed with each other. The output terminal of the driver DH is connected to a gate terminal of the semiconductor switch MH, and the output terminal of the driver DL is connected to a gate terminal of the semiconductor switch ML.
The logic circuit LC transforms the PWM pulse VPWM1 given by the PWM comparator COMP and delivers the PWM pulses VPWM2 to the driver DH and the driver DL. The logic circuit LC has functions, for example, to make the PWM pulse VPWM2 at a minimum pulse width before startup, to limit a duty ratio below 100% in the startup period, and to prevent the semiconductor switches MH and ML from simultaneously turning ON.
The DC to DC converter having the construction described above is in a stand-by state before its startup, and the discharge switch SW of the soft start circuit is in an ON state.
When the discharge switch SW is turned OFF to start the soft start operation at the time t1 indicated in FIG. 11, the capacitor CS is charged with a constant current from the constant current circuit IS and the terminal voltage VCS of the capacitor CS gradually increases. With gradual increase of the terminal voltage VCS, which is a target voltage, the error voltage VE delivered from the error amplifier EA likewise increases, which makes the duty ratio of the PWM pulse VPWM1 from the PWM comparator COMP increase slowly. Because the duty ratio of PWM pulse VPWM2 delivered by the logic circuit LC also increases gradually similarly to the PWM pulse VPWM1, the output voltage VOUT rises slowly. When the terminal voltage VCS of the capacitor CS becomes equal to the reference voltage VR at the time t2, the soft start operation is completed and the output voltage VOUT stops increasing and becomes a constant voltage. After completion of the startup, the output voltage VOUT is monitored by the resistors R1 and R2 and fed back as a feedback signal VFB to the error amplifier EA. The error amplifier operates with a target voltage of the reference voltage VR. When the output voltage VOUT changes, the error amplifier EA delivers an error voltage VE to compensate for the change, thereby controlling the output voltage VOUT at a constant voltage.
Before the startup at the time t1, the error amplifier EA in an actual operation thereof may deliver an error voltage VE not exactly equal to zero volts. As a consequence, the PWM comparator COMP delivers a PWM pulse VPWM1 with a duty ratio not larger than the minimum duty ratio at a frequency of the triangular signals VOSC. The PWM pulse VPWM1 is transformed to a PWM pulse VPWM2 with the minimum duty ratio by the logic circuit LC. This PWM pulse VPWM2 ON/OFF-controls the semiconductor switches MH and ML. Therefore, the DC to DC converter delivers a certain magnitude of output voltage VOUT=VO1 still before the startup at the time t1 as shown in FIG. 11. Although FIG. 11 is schematically depicted, in the constraint of representation with a drawing, with an exaggerated period of triangular waveform, an actual period corresponding to a single triangular waveform in the figure includes several tens to several thousands of triangular waves or pulses in actuality.
The operation delivering the voltage VO1 before startup can be advantageous in some cases. For example, in a case when a current signal detecting function, such as overcurrent protection, is provided, or in a case when a current mode control is conducted, the operation is beneficial. In these cases, pulses with at least a minimum pulse width may be continuously delivered in order for a current detecting function not to erroneously respond to a current surge in the switching time.
Even in the case the output of the voltage VO1 before startup is not advantageous, which means zero percent of the duty ratio of PWM pulses is desired, the circuit of FIG. 10 may unintentionally give a VPWM1 when an offset is generated at the input stage of the PWM comparator COMP due to variation in product characteristics. As a result, a non-zero volt voltage VO1 may be generated in the output voltage VOUT.
In the type of DC to DC converter having a construction continuously giving PWM pulses VPWM2 with a minimum duty ratio before startup, an unnecessary voltage VO1 is continuously applied to a load circuit connected to the output terminal before operation.
Accordingly, Patent Document 1 (identified further on) discloses a circuit construction to avoid generation of output voltage VOUT=VO1 before startup by inhibiting output of PWM pulse VPWM2 before startup. The following describes a construction of the startup circuit of the DC to DC converter disclosed in Patent Document 1.
FIG. 12 is a block diagram showing a construction of a startup circuit of the DC to DC converter disclosed in Patent Document 1. FIG. 13 shows waveforms of voltages in operation of the DC to DC converter using the startup circuit of FIG. 12. FIG. 12 omits the drivers DH and DL and the components in their downstream in FIG. 10. The components in FIG. 12 that are the same or equivalent to the components depicted in FIG. 10 are given the same symbol and detailed description thereon is omitted.
The startup circuit of FIG. 12 is provided with a logical product circuit AND at the output side of the logic circuit LC and a detecting circuit DET to detect the terminal voltage VCS of the capacitor CS. The logical product circuit AND is connected to the output terminal of the logic circuit LC at the first input terminal of the circuit AND, and is connected to the output terminal of the detecting circuit DET at the second input terminal of the circuit AND. The output terminal of the logical product circuit AND is connected to the input terminals of the drivers DH and DL and delivers a PWM pulse VPWM3, which is a logical product of the output of the logic circuit LC and the output of the detecting circuit DET. The logical product circuit AND is actually composed of two circuits, each delivering separately a pulse for the driver DH and a pulse for the driver DL.
The detecting circuit DET has a predetermined threshold value for detection, delivering a detection signal VD at a low level before the predetermined threshold value is reached by the terminal voltage VCS of the capacitor CS, and delivering a detection signal VD at a high level after the predetermined threshold value is exceeded by the terminal voltage VCS.
Before the startup time t1, which is indicated in FIG. 13, of the startup circuit, the detecting circuit DET delivers a detection signal VD at a low level. Consequently, the logical product circuit AND blocks the PWM pulse VPWM2 from the logic circuit LC. Just from the startup time t1 by opening the discharge switch SW to the time t3 at which the terminal voltage VCS of the capacitor CS reaches a predetermined threshold value, the detecting circuit DET continuously delivers a detection signal VD at a low level. Consequently, up to the time t3, the logical product circuit AND interrupt the PWM pulse VPWM3 that is to be given to the drivers DH and DL, and thus, the semiconductor switches MH and ML do not perform switching operation maintaining the output voltage VOUT at zero volts.
When the detecting circuit DET detects the terminal voltage VCS exceeding the predetermined threshold value, blockage by the logical product circuit AND is released, and the PWM pulse VPWM3 is permitted to be delivered to the drivers DH and DL. After that, switching operation is conducted according to the terminal voltage VCS of the capacitor CS as a target voltage for the output voltage VOUT. The output voltage VOUT increases gradually up to the time t2 at which the terminal voltage VCS reaches the reference voltage VR. After that, the output voltage VOUT is controlled at a constant voltage.
As described above, in this startup circuit, the output voltage VOUT is forcedly made to be zero volts, avoiding generation of the voltage VO1 despite output of the PWM pulse VPWM1 from the PWM comparator COMP before startup.